Hardware

Learn more about the options available in our hardware teams.

Architecture & Technology (ATG)

Central Engineering - CPU

Central Engineering - Systems

Partner Enablement Group (PEG)

Solutions Engineering - Implementation

Solutions Engineering - Physical IP

Solutions Engineering - SoC Engineering

Architecture & Technology (ATG)

(Part 1)

Location: Austin

Roles: Intern, Graduate

Length of Internship: 12 weeks

It is ATG’s mission to collaborate with teams inside, and outside, of Arm to provide leadership to the long-term (~10 year) architecture direction of Arm, our partners and the ecosystem. This is done through the creation and maintenance of compelling and innovative architectures; understanding, enabling and contributing to key industry trends that drive Arm’s business now and into the future; and helping shape the ecosystems to best serve Arm and its partnership.

About You

This role is suitable for someone with a combination of the following skills: A good understanding of concepts in computer architecture or engineering; strong C or C++ programming skills; understanding of computer microarchitecture, hardware design and validation; proficiency in a high-level shell or scripting language, such as Python; flexibility and a willingness to learn and improve new tools, collaborate and work effectively in a team; and the ability to communicate clearly with both expert and non-expert audiences.

Architecture & Technology (ATG)

(Part 2)

Location: Austin

Roles: Intern, Graduate

Length of Internship: 12 weeks

What could you be doing in this role?

Activities could include some of the following: Developing prototypes and models of hardware of software, evaluating prototype/model performance, developing tools, optimizing software performance, developing specifications and standards, contributing to open source projects, and spotting opportunities for innovative technology. When appropriate, this may include disseminating the results of work by writing blog posts and academic papers.

ATG Austin is a multidisciplinary group with teams working in a variety of areas:

Development of architecture specifications and standards, which includes creating models, software and RTL prototypes, and proof-of-concepts.
Development of test-generation solutions that enable our customers to validate their designs.
Research into trends in system architecture, security high performance computing, edge computing, and generative AI.

Central Engineering

Central Processing Unit (CPU)

(Part 1)

Location: Austin, Raleigh

Roles: Intern and Graduate

Length of Internship: 12 weeks

Arm CPUs are the heart of digital electronic devices. The CPU group develops and delivers all Arm CPU IP, from the applications processor in your phone to the real-time processor in your car and the microcontroller in every electronic gadget around you. We are a multidisciplinary group with several projects running in parallel, each project requiring hardware and software engineers with a variety of skillsets working closely together to produce ground breaking CPU products. CPU-Austin and CPU-Raleigh combined represent the Big-A CPU team. The Big-A CPU team delivers the highest performance (Arm Cortex-A and Arm Neoverse) processor implementations across all market segments, including IoT, automotive, mobile, client, and datacenter.

HW – Design: Build early prototypes, design micro-architecture, develop RTL using HDL languages (SystemVerilog) and scripting, and optimize PPAF (power, performance, area, frequency).
HW – Verification: Design and develop environments and test benches to verify functionality (architectural and micro-architectural), responsible for taking the design to tape-out quality. Might use one or more techniques (e.g. simulation/formal, pseudo-random/directed), using programming and scripting knowledge (e.g. SystemVerilog, C++, Python, assembly).
HW – Physical Implementation: Develop flows to turn IP into actual chips using scripting languages (e.g. Tcl/Python) and EDA tools (e.g. Cadence/Synopsys), to enable RTL optimization and PPA (power, performance, area) benchmarking.
HW-Performance Modelling: Measure and predict performance metrics across both existing designs, as well as model and study new cutting-edge micro-architectural ideas using internal and industry-standard benchmarks.

Central Engineering

Central Processing Unit (CPU)

(Part 2)

Location: Austin, Raleigh

Roles: Intern and Graduate

Length of Internship: 12 weeks

About You

This role suits someone who:

Enjoys working collaboratively as part of a team.
Enjoys finding creative solutions to complex technical problems.
Is interested in and wants to learn more about how computers/CPUs work.
Wants to develop skills in scripting, logic design, verification, and/or software programming.
Is studying electronic or computer engineering and similar subjects, either as part of a degree or as personal projects.
With RTL design, computer architecture and object oriented programming courses as a plus

What could you be doing in this role?

As an intern in the CPU group, you will have real responsibilities from day one, and you will get support and guidance from experts to help you succeed. Your work will contribute to current and future Arm CPU developments and power the next generation of digital devices. Through teamwork, training, and dedication to personal development, you can start your developmental journey to become a first-class Arm engineer.

Central Engineering

Systems

Location: Austin, Chandler

Roles: Intern and Graduate

Length of Internship: 12 weeks

Central Engineering Systems develops key IP in interconnect, memory controller, debug and trace, system controllers and IP tooling. Our team comprises seasoned professionals in the areas of RTL design, implementation, design verification, performance modeling, and software/tooling.

About You

This role suits someone with experience and expertise in computer architecture via formalized classwork and independent and/or academic projects. Our interns and graduates work in a range of disciplines, from back-end VLSI to front-end design and performance modeling. Candidates should have a broad understanding of digital system design and depending on the discipline, have capability in Verilog/SystemVerilog, C/C++, and Python/Perl.

What could you be doing in this role?

Graduates and Interns will be paired with a mentor who will guide them on their projects/tasks. Typical projects for interns could vary and include developing automation solutions, implementing new tests, and data analysis or detailed investigations of novel approaches to improve our existing processes.

Partner Enablement Group

Location: Austin

Roles: Intern

Length of Internship: 12 weeks

Partner Enablement Group (PEG) is Arm's engineering interface to customers all over the world. Experienced engineers in our group educate, train, support, and consult with Arm customers to ensure that Arm IP is used in an efficient, productive and timely manner to derive maximum benefit in customer applications. We also interface with internal engineering groups to represent customer needs. In the implementation support subgroup of PEG, we particularly focus on optimal physical design of customer silicon using Arm IP ranging from high performance cores to complex subsystems.

About You

This role suits someone with experience and expertise in physical implementation via formalized classwork and independent and/or academic projects. Candidates should have a broad understanding of IC back-end implementation, RTL design and gate level simulation. They should also have capability in scripting languages (Python/Perl) and EDA synthesis or place/route tools (Mentor, Cadence, Synopsys) in a Linux environment.

What could you be doing in this role?

In this role, you will work with a mentor to define a project that will not only demonstrate your knowledge of VLSI design but challenge you to the next level of understanding. You can expect to develop your back-end design skills while connecting front-end RTL, synthesis, power, timing and test for design closure. You will also collaborate with our team of creative and passionate engineers and work on actual cases from our customer base.

At the conclusion of your internship, you will give a short technical presentation on your project discussing what obstacles you encountered and how you overcame them as well as highlights of the cases you worked on.

_{Solutions Engineering Implementation}

_Location:_{Austin, San Jose and San Diego}

_Roles:_{Intern, Graduate}

_{Length of Internship:}_{12 weeks}

The Solutions Engineering organization delivers complex solutions from system specifications through front end and validation, pre-silicon simulation, physical implementation, GDS2, and silicon demonstrators.

The SE-Implementation team handles synthesis and place and route for good power, performance, area, yield, and time (PPAYT). It covers many functional disciplines from static timing analysis, constraint generation, physical verification, power intent, formal verification, power integrity, SoC integration, ECO, structured clocking, electrical signoff (eg IR/EM), DFT, EDA and methodology support for our flows and framework.

About You

An intern and graduate role is suitable for someone who has the ability to demonstrate you can express new insights and communicate them effectively. Also, you need to possess a high level of dedicated, initiative and problem-solving skills.

What could you be doing in this role?

You would be involved in any number of activities from block implementation (synthesis, place and route), data extraction and visualization, framework development

Solutions Engineering

SoC Engineering

(Part 1)

Location: Austin, Chandler

Roles: Intern, Graduate

Length of Internship: 12 weeks

The Solutions Engineering (SE) team builds compute systems and SoC’s that integrate Arm IP, including CPU, GPU, NPU, and system IP. Our systems target different market domains, ranging from mobile phones, loT devices, and datacenters to autonomous driving.

The FE team within SE is responsible for micro-architecting the system based on requirements and creating the system logical RTL with all IPs integrated, ensuring it is high performant and meets the area and power targets. It also performs robust system verification to help ensure it functions as expected and meets the quality standard expected.

The IMPL team within SE transforms the logical RTL into physical layout using scripting languages (Tcl, Python) and EDA tools (Siemens, Synopsys, Cadence). The final physical layout must meet floorplan, timing, and foundry design rules and is shipped to a foundry for manufacturing into an SoC.

About You

This role is suitable for someone who:

Enjoys being part of a diverse team.
Enjoys writing code to provide elegant solutions to complex problems.
Understands hardware description language (Verilog/VHDL) for hardware roles.
Understands object-orientated programming.

What could you be doing in this role?

As an intern or graduate in Solutions Engineering, you will be working as part of a team building or verifying complex compute systems and SoC’s. You will play a key part in our team from day one, receiving mentoring and support from our experts to help you succeed.

Solutions Engineering

Physical IP

(Part 1)

Location: Austin

Roles: Intern and Graduate

Length of Internship: 12 weeks

Our physical IP group within Solutions Engineering comprises some of the industry’s leading experts in deep submicron circuit design. This position is a rare opportunity for you to work with our standard cell design and layout teams. You will work on the newest technology nodes while collaborating with our team on many different types of logic circuits.

About You

This role suits someone with the following skills:

Fundamental understanding of MOSFET electrical characteristics and transistor level device physics.
Understanding of layout and circuit design to collaborate with the mask design and engineering teams.
Transistor level spice simulators, e.g. HSPICE, Spectre.
Transistor level design of static circuits, including state retaining elements like latches and flops.
An understanding of power, performance, and area tradeoffs at the cell and block level.
Understanding or an ability to learn industry standard modeling formats, including Liberty (NLM, CCS, and LVF), Verilog, LEF, NDM, SPICE, and APL.
Programming and scripting skills in UNIX, Perl, Python, C++, or similar language.
Ability to debug intricate issues and clearly summarize and report the status to colleagues.

Solutions Engineering

Physical IP

(Part 2)

Location: Austin

Roles: Intern and Graduate

Length of Internship: 12 weeks and 6 months

What could you be doing in this role?

The successful candidate will work with a small team of experienced integrated circuit design engineers to:

Develop standard cell libraries in the newest technology nodes.
Optimize schematics in close cooperation with the layout team.
Generate all standard cell library views.
Verify all views by using them in a variety of standard tool flows.